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LSIs for Compact Disc/CD-ROM Player
MN662792AB
1. Overview
MN662792AB is a signal processing IC for CDs. This IC integrates an optical servo (focus, tracking, and traverse servos) processing function, digital signal processing function (EFM demodulation and CIRC/CD-ROM error correction), digital servo processing function for spindle motor, anti-shock memory control function supporting 64-Mbit, 16-Mbit, 4-Mbit, or 1-Mbit DRAM that enables compression/decompression for a disc rotation synchronous playback (i.e., jitter free), a decode function for MP3/WMA, Fs conversion processing function, a digital filter, and D/A converter. All the processing functions after the head amplifier (RF amplifier) are integrated into a single chip. This IC includes Microsoft's technology and cannot be used and distributed without a license from Microsoft Corporation.
: WINDOWS MEDIA AUDIO (WMA) Windows Media is trademark, or registered trademark of Microsoft Corporation in the United States and/or other countries.
2. Functions and Features
(Optical servo) * Focus (Fo), tracking (Tr), and traverse (TRV) servos * Automatic adjustment functions (Fo/Tr gain, Fo/Tr offset, Fo/Tr balance) * Provided with a countermeasure for dropout * Provided with an anti-shock function * Provided with a track-cross detection function * Drive output PWM drive function supported * Provided with supply voltage monitoring and a servo gain automatic adjustment function (Digital signal processing) * Containing DSL and analog/digital PLL * Provided with a frame synchronous detection/protection/interpolation * Subcode data processing Q-data CRC check On-chip Q-data register On-chip CD-TEXT data register
Publication date: October 2002
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MN662792AB
* CIRC error correction C1 decoder: double error correction C2 decoder: triple/quadruple error correction On-chip deinterleaving 16K RAM * CD-ROM error correction Q decoder: an error correction P decoder: an error correction Mode1 and Mode2 compatible * Audio data interpolation processing 4-sampling average value interpolation and previous value hold (Spindle motor servo) * CLV digital servo * Servo gain setting function * Shaft loss compensation setting function (Audio circuit) * Soft muting * Digital attenuation (2048 levels) * Soft attenuation (2048 levels) * Digital audio interface (EIAJ format) * 8 x oversampling digital filter * On-chip low-voltage op amp * Bass boost filter, high-band notch filter, and surround function * On-chip digital de-emphasis (MP3 decoding) * Decoding of signals recorded in MPEG1-layer3 or MPEG2-layer3 format * Decoding of signals recorded in MPEG1-layer2 or MPEG2-layer2 format * Decoding of signals recorded in MPEG2.5 format * Sampling rate conversion from signals recorded at Fs=32 kHz or 48 kHz to 44.1 kHz
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MN662792AB
(WMA decoding) * Decoding of signals recorded in WMA Ver.8 format (Sampling rate: 48 kHz to 22.05 kHz) * Supporting special playback (forward, reverse, and resume playback) (SD interface) * Stream serial input from SD available (Anti-shock memory controller) * ADPCM 4-bit compression or expansion/decompression in full-bit (16 bits) mode * External DRAM selectable 64-Mbit DRAM (16M addresses x 4 bits) x 1 16-Mbit DRAM (4M addresses x 4 bits) 16-Mbit DRAM (4M addresses x 4 bits) 16-Mbit DRAM (4M addresses x 4 bits) 4-Mbit DRAM (1M addresses x 4 bits) 4-Mbit DRAM (1M addresses x 4 bits) 1-Mbit DRAM (256 addresses x 4 bits) 1-Mbit DRAM (256 addresses x 4 bits) (Others) * Disc rotation mechanism has a synchronous playback (jitter-free) mode (-50% to +50%) * 4 x speed playback (when using jitter-free function) * TX output (1 x , 2 x , and 3 x speed) supported * Serial data output pitch shift function x2 x1 x1 x2 x1 x2 x1 + 4-Mbit DRAM (1M addresses x 4 bits) x 1
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MN662792AB 3. Pin Assignment
80-pin flat package (LQFP080-P-1414A)
ADPVCC IOVDD2
* EXT1 * EXT0 * EXT2 * FLAG
TMOD2
DVDD3
AVDD1
DVSS3
AVSS1
AVSS2
AVDD2
PLLF0
RFSW
OUTR
OUTL
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 MCLK MDATA MLD 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 DRVDD 2 D0 3 D1 4 NWE 5 NRAS 6 D2 7 D3 8 NCAS0 9 10 11 12 13 14 15 16 17 18 19 20 A8 A7 A6 A5 A4 A9 A0 A1 A2 40 39 38 37 36 35 34 33 32 IREF ARF LDON BDO NRFDET OFT RFENV TE FE FBAL TBAL IOVDD1
* BLKCK *
SMCK SBCK STAT NRST
PWMSEL
* SPPOL * PMCK * DQSY * TXTD * TXTCK
NTEST X2 X1 DVSS1 DVDD1
MN662792AB
DSLF
TX
PLLF
31 30 29 28 27 26 25 24 23 22 21
* * *
FOM FOP TRM TRP TRVM TRVP SPOUT DVDD2
* MON
* NCAS1
A3
Note) Pins marked with an asterisk can be switched to different signals by using microcontroller commands.
DVSS2
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MN662792AB 4. Block Diagram
MDATA MCLK MLD STAT PMCK SMCK AVDD2 AVSS2 IREF ARF DSLF RPSW PLLF PLLF0
DVDD DVSS
TIMING GENERATOR
X2 X1 A/D CONVERTER
MICROCONTROLLER INTERFACE
DSL, PLL, VCO SUBCODE INTERFACE
ADPVCC FE TE RFENV
SPINDLE SERVO
MP3 DECORDER
EFM DEMODULATION SYNC INTERPOLATION CIRC ECC CDROM ECC
TXTCK TXID DQSY SBCK SUBC (TXID/SMCK) NCLDCK (DQSY) FLAG BLKCK
CIRC RAM DRVDD
DSV OFT NRFDET BDO
PS CONVERTOR BUS CONTROL UNIT (BCU) ADPCM ANALOG LOW PASS FILTER SERIAL OUTPUT INTERFACE (DAO)
LRCK (TXTCK/EXT1) BCLK (DQSY/EXT2) SRDATA (TXID/EXT0) IPFLAG (FLAG)
SERVO CPU
DIGITAL FILTER D/A CONVERTER
DRAM INTERFACE
A9 to A0 NRAS NCAS0 NCAS1 NWE D3 to D0
INPUT PORT
DIGITAL OUT
PWMSEL SPPOL
OUTPUT PORT
TX SPOUT TRVP TRVM TRP TRM FOP FOM TBAL FBAL LDON
OUTL OUTR AVDD1 AVss1
LRCKIN (EXT1) BCLKIN (EXT2) SRDATAIN (EXT0)
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MN662792AB 5. Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol DRVDD D0 D1 NWE NRAS D2 D3 NCAS0 *NCAS1 A8 A7 A6 A5 A4 A9 A0 A1 A2 A3 DVSS2 DVDD2 SPOUT TRVP *TRVM TRP TRM * FOP FOM * IOVDD1 TBAL FBAL FE TE RFENV OFT NRFDET BDO LDON ARF IREF I/O I I/O I/O O O I/O I/O O O O O O O O O O O O O I I O O O O O O O I O O I I I I I I O I I Function Power supply for DRAM interface (Pins 2 to 19 and 80) DRAM data I/O signal 0 DRAM data I/O signal 1 DRAM write enable signal DRAM RAS control signal DRAM data I/O signal 2 DRAM data I/O signal 3 DRAM CAS control signal 0 DRAM CAS control signal 1 DRAM address signal 8 DRAM address signal 7 DRAM address signal 6 DRAM address signal 5 DRAM address signal 4 DRAM address signal 9 DRAM address signal 0 DRAM address signal 1 DRAM address signal 2 DRAM address signal 3 Ground for digital circuits Power supply for digital circuits Spindle motor drive signal output (absolute value output) Traverse drive output (positive polarity output) Traverse drive output (negative polarity output) Tracking drive output (positive polarity output) Tracking drive output (negative polarity output) Focus drive output (positive polarity output) Focus drive output (negative polarity output) Power supply for I/O Tracking balance adjustment output Focus balance adjustment output Focus error signal input (analog input) Tracking error signal input (analog input) RF envelope signal input (analog input) Off-track signal input High: Off-track RF detection signal input Low: Detection Dropout signal input High: Dropout Laser ON signal output High: ON RF signal input Reference current input
Note) Pins marked with an asterisk can be switched to different signals by using microcontroller commands.
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MN662792AB
Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Symbol ADPVCC DSLF RFSW PLLF PLLFO AVDD2 AVSS2 OUTL AVSS1 OUTR AVDD1 DVSS3 DVDD3 TMOD2 FLAG *
I/O I O I O O I I O I O I I I I O I/O I/O I/O I O I I I O I O I/O O I O O O O O I O I I I O
Function Voltage input for supply voltage monitor (analog input) DSL loop filter DSL loop filter PLL loop filter PLL loop filter Power supply for analog circuits (for DSL, PLL, and A/D) Ground for analog circuits (for DSL, PLL, and A/D) L-ch audio output Ground for analog circuits (for audio output stage) R-ch audio output Power supply for analog circuits (for audio output stage) Ground for digital circuits Power supply for digital circuits Test input pin Low: Normal Flag signal output Expansion I/O port 2 Expansion I/O port 0 Expansion I/O port 1 Power supply for I/O Digital audio interface output signal Microcontroller command clock signal input Microcontroller command data signal input Microcontroller command load signal input Low: Load Subcode block clock signal (f=75 Hz in normal-speed playback mode) PWM output mode selection input Low: Direct High: 3-state 4.2336 MHz/8.4672 MHz clock signal output Clock input for subcode serial output Status signal output Reset input Low: Reset Spindle motor drive signal output (polarity output) 88.2-kHz clock signal output Pack signal output for CD-TEXT data CD-TEXT data signal output External clock signal input for CD-TEXT register Test input pin High: Normal Crystal oscillator circuit output pin (f=16.9344 MHz, 33.8688 MHz) Crystal oscillator circuit input pin (f=16.9344 MHz, 33.8688 MHz) Ground for digital circuits Power supply for digital circuits Monitor for evaluation
*EXT2 *EXT0 *EXT1
IOVDD2 TX MCLK MDATA MLD BLKCK * PWMSEL SMCK *
*SBCK
STAT NRST SPPOL *
*PMCK *DQSY *TXTD *TXTCK
NTEST X2 X1 DVSS1 DVDD1 MON *
Note) Pins marked with an asterisk can be switched to different signals by using microcontroller commands.
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MN662792AB 6. List of the Selection Pins
A. List of the selection pins
Pin No. 9 24 26 28 55 56 57 58 64 66 67 70 71 72 73 74 80
Initial setting signal
Selection signal A10 PC EXT4 EXT3 MON2 SRF MON3 VDET LRCK ZBLKCK SUBC WAIT CK16M (see note 1) SBLKCK BCLK SUBC PCK NCAS1
NCAS1 TRVM TRM FOM FLAG EXT2 EXT0 EXT1 BLKCK SMCK SBCK SPPOL PMCK DQSY TXTD TXTCK MON
TXNCLDCK BCLKIN SRDATAIN PCK VAL DQSY
NRQ BCLK SRDATA CK16M SSYNC
EXSCK STRIN CK8M DABLKCK
LRCKIN
TXNCLDCK VDET LRCK A11
NCLDCK SRDATA
SRF
Note 1) The CK16M is output with PWMSEL set to high and D15 of 4Eh command set to 1. Note 2) The others are selected by using the microcontroller command.
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MN662792AB
B. Signal descriptions
Signal name MON2 MON3 BCLKIN SRDATAIN LRCKIN BCLK SRDATA LRCK SSYNC DABLKCK ZBLKCK TXNCLDCK NCLDCK SBLKCK SUBC CRC RESY FCLV BSSEL FLAG0 IPFLAG1 IPFLAG2 FLAG6 A10 A11 NCAS1 CLVS PC VDET NFLOCK NTLOCK SENSE PCK SRF CK16M CK8M EXT3 EXT4 WAIT NRQ STRIN VAL EXSCK I/O O O I I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O I I I Function Fixed for evaluation / Serial monitor signal output 2 Fixed for evaluation / Serial monitor signal output 3 Bit clock signal input for serial data Serial data signal input L/R identification signal input Bit clock signal output for serial data Serial data signal output L/R identification signal output CD-ROM sector sync signal output Block clock signal output after adding the track buffer Interpolation block clock signal output (f=75 kHz in normal-speed playback mode) Subcode serial output sync frame clock Subcode frame clock signal output (f=7.35 kHz in normal-speed playback mode) Subcode serial output sync block clock Subcode serial output Subcode CRC check result output High: OK Low: NG Frame re-sync signal High: Synchronous Low: Asynchronous Frame sync detection signal High: Detection Low: No detection PLL frequency pull-in operating signal Low: Pulling in C1 error detection flag output signal High: Detection Interpolation flag signal output High: Interpolation (synchronized with serial output only when in MSOFF.) Compatible with conventional products Interpolation flag signal output High: Interpolation (synchronized with disc rotation when in MSON.) Address reset signal for error correction de-interleave RAM Low: Address reset generated DRAM address A10 signal output DRAM address A11 signal output (available when 64M DRAM mode is used.) CAS control signal when 16M+16M, 16M+4M, 4M+4M, or 1M+1M DRAMs are used Spindle servo operating condition output signal High: CLV Low: Rough servo Spindle motor ON signal output Low: ON Vibration detection signal output High: Detection Focus servo pull-in signal Low: Pull-in state Tracking servo pull-in signal Low: Pull-in state Sense signal output PLL extraction clock output (f=4.3218 MHz in normal-speed playback mode) DSL comparator output signal 16.9344-MHz clock signal output 8.4672-MHz clock signal output Expansion output port 3 Expansion output port 4 WAIT signal output for DRAM data reading SD bit stream input request signal output SD audio bit stream serial input signal SD bit stream input enable signal SD bit stream data input clock signal
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MN662792AB Electrical Characteristics A. ABSOLUTE MAXIMUM RATINGS
Parameter A1 A2 Supply voltage Internal supply voltage Input voltage Symbol DRVDD IOVDD1,2 AVDD1,2 DVDD1,2,3 Rating -0.3 to +4.6 -0.3 to +4.6 DVSS-0.3 to DRVDD+0.3 DVSS-0.3 to IOVDD+0.3 AVSS-0.3 to AVDD1+0.3 AVSS-0.3 to AVDD2+0.3 DVSS-0.3 to DRVDD+0.3 DVSS-0.3 to IOVDD+0.3 AVSS-0.3 to AVDD1+0.3 AVSS-0.3 to AVDD2+0.3 570 -30 to +85 -50 to +125 Unit V V Note DVSS1,2=0 V AVSS1,2=0 V DVSS1,2=0 V AVSS1,2=0 V DVSS1,2=0 V AVSS1,2=0 V
A3
VI
V
A4
Output voltage
VO
V
DVSS1,2=0 V AVSS1,2=0 V DVSS1,2=0 V AVSS1,2=0 V
A5 A6 A7
Power dissipation Operating ambient temperature Storage temperature
PD Topr Tstg
mW C C
Note 1) The absolute maximum ratings are the limit values beyond which the IC may be broken. They do not assure operations. Note 2) Connect each of the DVSS1, DVSS2, AVSS1, and AVSS2 pins directly to ground and use at the same voltage. Note 3) Connect each of the DRVDD, IOVDD1, IOVDD2, AVDD1, and AVDD2 pins directly to the specified power supply and use at the same voltage. Note 4) DVDD1, DVDD2, DVDD3, DRVDD, IOVDD1, IOVDD2, AVDD1, and AVDD2 should be powered up at the same time. Note 5) Connect a bypass capacitor of 0.1 F or larger between each of the power supply pins and ground.
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MN662792AB B. OPERATING CONDITIONS
DVSS1,2=0 V AVSS1,2=0 V Topr=-30C to +85C Parameter B1 B2 I/O system supply voltage Digital system supply voltage Symbol IOVDD1,2 DVDD1,2,3 DVDD1,2,3 B3 B4 B5 Audio system supply voltage Analog system supply voltage D-RAM interface voltage AVDD1 AVDD2 DRVDD MP3, WMA : ON MP3, WMA: OFF
Conditions Min 2.2 1.65 1.50 2.7 2.7 2.2
Limits Typ 3.3 1.8 1.8 3.3 3.3 3.3 Max 3.6 2.7 2.7 3.6 3.6 3.6
Unit V V V V V V
Note 6) Each operation of the digital system supply voltages, DVDD1, DVDD2, and DVDD3, is guaranteed only when the voltages are lower than the other supply voltages, IOVDD1, IOVDD2, AVDD1, AVDD2, and DRVDD.
: WINDOWS MEDIA AUDIO (WMA) Windows Media is trademark, or registered trademark of Microsoft Corporation in the United States and/or other countries.
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter Symbol Conditions Min Self-excited Oscillation 1 (Note 7) B6 B7 B8 B9 Oscillator frequency Recommended external capacitance 1 Recommended external capacitance 2 Recommended external feedback resistance fxtal C1 C2 R1 16.9344-MHz Xtal 16.9344 47 pF 47 470 k MHz Limits Typ Max Unit
Self-excited Oscillation 2 (Note 7) B10 B11 B12 B13 Oscillator frequency Recommended external capacitance 1 Recommended external capacitance 2 Recommended external feedback resistance fxtal C1 C2 R1 33.8688-MHz Xtal 33.8688 10 pF 10 4.7 k MHz
Note 7) Oscillation circuit
X2 MN662792AB X1
R1
C2 xtal C1
Values for C1 and C2 specified above are standard values. The appropriate capacitors' values differ according to the crystal oscillator used. Use the values specified by the crystal oscillator manufacturer.
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MN662792AB C. ELECTRICAL CHARACTERISTICS
(1) DC Characteristics Parameter C1 C2 C3 C4 C5 C6 C7 C8 C9 Supply current I/O / analog system supply current Total power consumption Supply current I/O / analog system supply current Total power consumption Supply current I/O / analog system supply current Total power consumption Symbol IDD(D) IDD(A) PT IDD(D) IDD(A) PT IDD(D) IDD(D) PT DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Limits Min Anti-shock memory function used. No external load connected. (in 2x-speed playback mode) MP3 decode: OFF CD-ROM decode: OFF Digital PLL: OFF Anti-shock memory function used. No external load connected. (in 4x-speed playback mode) MP3 decode: ON CD-ROM decode: ON Digital PLL: OFF Anti-shock memory function used. No external load connected. (in 4x-speed playback mode) WMA decode: ON CD-ROM decode: ON Digital PLL: OFF Typ 25 12 84.6 50 20 156.0 56 23 176.7 Max 50 mA 24 169.2 100 mA 40 312.0 100 mA 40 312.0 mW mW mW
Conditions
Unit
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter Input Pins (1) C10 C11 C12
1
Symbol
Conditions Min
Limits Typ Max
Unit
High-level input voltage Low-level input voltage Input leakage current
2
VIH1 VIL1 ILK1 VIN=0 V or 3.3 V
2.31 0.00
3.30 0.99 1
V V A V V A
Input Pins (2) C13 C14 C15 1 2
High-level input voltage Low-level input voltage Input leakage current
VIH2 VIL2 ILK2 VIN=0 V or 3.3 V
2.31 0.00
3.30 0.99 1
D0, D1, D2, D3 PWMSEL, TMOD2, EXT0, EXT1, EXT2, OFT, NRFDET, BDO, NTEST, MCLK, MDATA, MLD, NRST, SBCK, TXTCK
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter Output Pins (1) C16 C17
3
Symbol
Conditions Min
Limits Typ Max
Unit
High-level output voltage Low-level output voltage
4
VOH1 VOL1
IOH1=-1.0 mA IOL1=1.0 mA
2.7 0.4
V
Output Pins (2) C18 C19
High-level output voltage Low-level output voltage
5
VOH2 VOL2
IOH2=-1.0 mA IOL2=1.0 mA
2.7 0.4
V
Output Pins (3) C20 C21 C22 3 4 5
High-level output voltage Low-level output voltage Output leakage current
VOH3 VOL3 OLK3
IOH3=-1.0 mA IOL3=1.0 mA
2.7 0.4
V A
Hi-Z state 1 VO=0 V or 3.3 V D0, D1, NWE, NRAS, D2, D3, NCAS0, NCAS1, A8, A7, A6, A5, A4, A9, A0, A1, A2, A3, MON TRVM, TRM, FOM, LDON, FLAG, EXT0, EXT1,EXT2, TX, BLKCK, STAT, SPPOL, PMCK, SMCK, DQSY, TXTD SPOUT, TRVP, TRP, FOP
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter Analog System Input Pin 1: C23 Input current ARF VARF RARF EFM signal input level in an application circuit of DSL block. REGSEL: R1+R2+R3 setting REGSEL: R2+R3 setting REGSEL: R3 setting 0.5 65 26 13 1.0 100 40 20 135 54 27 1.0 200 V[p-p] k IREF IREF When pulled with an 82-k resistor. 19 28 37 A Symbol Conditions Min Limits Typ Max Unit
Analog System Input Pin 2: C24 C25 Input signal amplitude Internal resistance between ARF and DSLF pins
Analog System Input Pin 3: C26 C27 Input leakage current Internal resistance between ARF and RFSW pins
RFSW ILKR RRFSW TE, FE, RFENV, ADPVCC VIH4 VIL4 0.33 2.97 V A k
Analog System Input Pin 4: C28 C29
High-level input voltage Low-level input voltage
A/D Converter (for servo) C30 C31 C32 Resolution Integral nonlinearity Differential nonlinearity RES INL DNL A/D output =99 to 66 (2's complement) 8 2 3 bit LSB
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter Symbol Conditions Min Analog System Output Pin 1: DSLF (IREF pin is pulled up to AVDD2 with an 82-k resistor) C33 C34 C35 Output current (N) Output current (P) Output unbalance current Phase comparator output current (N) Phase comparator output current (P) Input leakage current Output unbalance current VCO oscillator frequency for PLL Output current (N) Output current (P) Input leakage current IDSH IDSH IDSEL BDO: Low, Tracking ON state DSLF=1.65 V BDO: Low, Tracking ON state DSLF=1.65 V BDO: Low, Tracking ON state Normal current mode 59 -111 -7 85 -85 0 111 -59 7 A Limits Typ Max Unit
Analog System Output Pin 2: PLLF (IREF pin is pulled up to AVDD2 with an 82-k resistor) C36 C37 C38 C39 C40 IPFH IPFH ILKP IPLBL fVCO1 PLLF=1.65 V PLLF=1.65 V Hi-Z state PLLF=1.65 V -10 12.96 0 59 -111 85 -85 111 -59 1.0 10 69.17 MHz A
Analog System Output Pin 3: PLLFO (IREF pin is pulled up to AVDD2 with an 82-k resistor) C41 C42 C43 IPFHO IPFHO ILKPO Hi-Z state 63 -117 90 -90 117 -63 1.0 A
Analog System Output Pin 4: TBAL, FBAL (IREF pin is pulled up to AVDD2 with an 82-k resistor) C44 C45 Output current (N) Output current (P) IBAH IBAL At default setting (x1) At default setting (x1) 17 -33 25 -25 33 -17 A
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V
3.3 V 82 k 0.1 F VARF 1000 pF ARF 100 k RFSW DSLF 0.022 F IREF
1.0 V[p-p] (TYP)
PLLF 560 1000 pF 0.12 F PLLFO
Recommended Circuit for DSL and PLL Blocks Note 8) The above is a basic circuit. Calculate the constants and other factors of the circuit in consideration of playability when making use of this circuit for actual applications.
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter Symbol Conditions Min D/A Converter Analog Characteristics (Notes 9 and 12) C43 C44 C45 C46 C47 C48 Signal-to-noise ratio Dynamic range Total harmonic distortion ratio Crosstalk Output level 1 Output level difference S/N D.R. THD+N EIAJ EIAJ EIAJ EIAJ 1 kHz F.S. (Note 10) Difference between OUT and OUTR pins at output level 20 log (VR/VL) 70 1.04 -0.99 90 80 97 88 0.02 80 1.33 1.62 +0.99 0.04 dB dB % Limits Typ Max Unit
dB
Vrms dB
C49 Output level 2 1 kHz F.S. (Note 11) 0.69 0.88 1.07 Vrms Note 9) The analog characteristics show the measured values when inserting 15- resistor between AVDD1 and power supply. The above typical values are only reference values and not guaranteed. Note 10) The output level 1 shows the measured value at the output pin of the application circuit below. Note 11) The output level 2 shows a value at the output pin of the IC and is calculated by taking the measured value of output level 1, dividing it by the circuit gain. Note 12) With no anti-shock memory function used, the operation of the D/A converter will not be guaranteed in modes other than normal-speed playback.
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DRVDD 100 pF 22 F 47 k + 100 pF 1.5 k 2.2 k 0.001 F 560 47 k 22 F + 47 k 47 k 0.0018 F 15 1 k
MN662792AB
IOVDD
AVDD2
DVDD
AVDD1
DRVDD1 IOVDD1
IOVDD2
AVDD2 DVDD1 DVDD2
[ Application Circuit with D/A Converter ]
OUTL AVDD1 AVSS1 OUTR
100 F + - 0.1 F
MN662792AB
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100 pF 1 k + 0.0018 F 22 F 47 k 47 k 100 pF 47 k + 22 F 560 47 k 1.5 k 2.2 k 0.001 F
DVSS1
DVSS2
AVSS2
DVSS1
AVSS2
AVSS1
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MN662792AB
(2) AC Characteristics DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter Reset Timing (Note 13) C50 NRST pulse width TNRSTL 200 s 15 30 mV[p-p] mV[p-p] Symbol Conditions Min Limits Typ Max Unit
Power Supply Ripple Noise (Note 14) C51 C52 Ripple amplitude Ripple noise amplitude Note 13) VRIP VNZ
When the power is turned on, reset with the NRST pulse which is equal to or exceeds the above pulse width only after the clock oscillation is stabilized within 10% of error of the specified oscillator frequency.
TNRSTL NRST
0.2 VDD
0.2 VDD
Note 14) The standard ripple noise values of the IC are guaranteed on condition that the values apply to typical 50Hz to 100-Hz ripples with 500-kHz typical noise and that both the ripples and noise are in sine waveform as shown below. The values, however, vary under the influence of other parts located on the PCB. Therefore, be sure to apply the IC to practical applications and check the actual ripple noise values.
Noise frequency: 500 kHz
VRIP Ripple frequency: 50 Hz to 100 Hz
VNZ
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter Transition Time 1 (Note 15) C53 C54 Rise time Fall time TR1 TF1 250 250 ns ns Symbol Conditions Min Limits Typ Max Unit
Transition Time 2 (Note 16) C55 Rise time TR2 TF2 50 50 ns ns
C56 Fall time (Note 15) MCLK, MLD (Note 16) SBCK, TXTCK
0.7 IOVDD 0.3 IOVDD TR1 , TR2
0.7 IOVDD 0.3 IOVDD TF1 , TF2
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter Microcontroller Command Input Timing C57 C58 C59 C60 C61 C62 C63 Clock frequency Clock pulse width Data setup time Data hold time MLD delay time Latch pulse time MCLK delay time fMCLK TCH,CL TDSU TDH TLDD TLDW TCKD 300 300 300 300 0.5 300 10 1.1 MHz ns ns ns ns s ns Symbol Conditions Min Limits Typ Max Unit
1/fMCLK
MCLK
TCH
TCL
MDATA TDSU MLD TDH
TLDD
TLDW
TCKD
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter Symbol Conditions Min Subcode Interface (SBCK, TXTD (SUBC), DQSY (NCLDCK)) C64 C65 C66 C67 C68 Clock width High-level pulse width Low-level pulse width Delay time Setup delay time TCK TCKH TCKL TSBD TSD When noise filter is used. When no noise filter is used. 909 400 400 350 173 150 ns ns ns ns ns ns Limits Typ Max Unit
TCK TCKL SBCK TCKH SUBC
(Output from TXTD)
TSD NCLDCK
(Output from DQSY)
TSBD
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter Subcode Interface (TXTCK, TXTD, DQSY) C69 C70 C71 C72 C73 Clock width High-level pulse width Low-level pulse width Delay time Setup delay time TCK TCKH TCKL TSBD TSD 2500 1200 1200 1150 1100 ns ns ns ns ns Symbol Conditions Min Limits Typ Max Unit
TCK TCKH TXTCK TCKL
TXTD TSD TSBD
DQSY
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter Symbol Conditions Min Stream Interface (STRIN, EXSCK, VAL, NRQ) C74 C75 C76 C77 C78 C79 Clock frequency High-level pulse width Low-level pulse width Hold time Setup time Delay time TCEXTCK
TWHEXTCK TWLEXTCK
Limits Typ Max
Unit
10 50 50 40 10 0
MHz ns ns ns ns ns
THISTR TSISTR TDOSTR TCEXTCK
EXSCK TWHEXTCK TWLEXTCK
STRIN VAL TSISTR THISTR
NRQ TDISTR
(Note 17) EXSCK, STRIN, and VAL are input from EXT2 (EXSCK), EXT0 (STRIN), and VAL (EXT1) pins respectively. NRQ is output from FLAG (NRQ) pin.
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter STAT Output Interface C80 C81 C82 C83 Clock width High-level pulse width Low-level pulse width Delay time TMT TMTH TMTL TMTD When noise filter is used. When no noise filter is used. 909 400 400 350 173 ns ns ns ns ns Symbol Conditions Min Limits Typ Max Unit
TMT MCLK TMTL TMTH
STAT
TMTD
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter D/A Output Interface 1 C84 C85 C86 C87 C88 Clock width High-level pulse width Low-level pulse width Setup time Hold time TBCLK TBCLKH TBCLKL TST THD In normal-speed playback mode 70 70 354 177 177 ns ns ns ns ns Symbol Conditions Min Limits Typ Max Unit
D/A Output Interface 2 C89 C90 C91 C92 C93 Clock width High-level pulse width Low-level pulse width Setup time Hold time TBCLK TBCLKH TBCLKL TST THD In 4x-speed playback mode 30 30 118 59 59 ns ns ns ns ns
D/A Output Interface TBCLKL
TBCLK
TBCLKH
BCLK
SRDATA LRCK
TST
THD
(Note 18) SRDATA, BCLK, and LRCK are output in combination with DQSY (BCLK), TXTD (SRDATA), and TXTCK (LRCK) or EXT0 (SRDATA), EXT1 (LRCK), and EXT2 (BCLK).
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V Parameter D/A Converter Input Timing C94 C95 C96 C97 C98 C99 BCLK frequency SCLK pulse width Data setup time Data hold time LRCK frequency BCLK-LRCK timing fBCLK TCH,CL TDSU TDH fLRCK TBL,TLB 100 100 100 100 44.1 2.8 ns ns ns ns kHz ns Symbol Conditions Min Limits Typ Max Unit
1/fBCLK
BCLKIN TCH SRDATAIN TDSU LRCKIN TBL TLB TBL TLB TDH TCL
1/fLRCK
(Note 19)
SRDATAIN, LRCKIN, and BCLKIN are input from EXT0 (SRDATAIN), EXT1 (LRCKIN), EXT2 (BCLKIN) respectively.
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V (In BCKSEL=0 mode) Parameter DRAM Interface C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 Read/Write Cycle tASR tRAH tASC tCAH tRCD tRAC tCAC tWCS tWCH tDWDS tDWDH 2 1 1 2 2 4 2 2 2 1 2 cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle Symbol Conditions Min Limits Typ Max Unit
A0 to A11 row address setup time A0 to A11 row address hold time A0 to A11 column address setup time A0 to A11 column address hold time RAS-CAS delay time (NCAS0, NCAS1) RAS access time CAS access time Write enable signal NWE setup time Write enable signal NWE hold time D0 to D3 write data setup time D0 to D3 write data hold time Page Mode Data Transfer
DRAM Interface C111 C112 C113
CAS pre-charge pulse width CAS low-level pulse width RAS hold time
tCP tCAS tRSH
1 2 2
cycle cycle cycle
DRAM Interface CAS Before RAS Refresh C114 C115 C116 CAS-RAS delay time Refresh RAS low-level pulse width tCRD tRRAS 1 4 cycle cycle cycle
Refresh CAS low-level pulse width tRCAS 5 A11 and A10 indicate the output from MON pin and NCAS1 pin respectively. One cycle is the system clock cycle of 1 / (16.9344 MHz or 33.8688 MHz) [s]. The system clock frequencies, 16.9344 MHz and 33.8688 MHz, are determined according to the IC's DRAM interface clock frequency.
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MN662792AB
DVDD1,2,3=1.8 V, DRVDD=3.3 V, IOVDD1,2=3.3 V, DVSS1,2=0 V AVDD1=3.3 V, AVDD2=3.3 V, AVSS1,2=0 V (In BCKSEL=1 mode) Parameter DRAM Interface C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 Read/Write Cycle tASR tRAH tASC tCAH tRCD tRAC tCAC tWCS tWCH tDWDS tDWDH 2 1 1 1 2 4 1 2 1 1 1 cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle Symbol Conditions Min Limits Typ Max Unit
A0 to A11 row address setup time A0 to A11 row address hold time A0 to A11 column address setup time A0 to A11 column address hold time RAS-CAS delay time (NCAS0, NCAS1) RAS access time CAS access time Write enable signal NWE setup time Write enable signal NWE hold time D0 to D3 write data setup time D0 to D3 write data hold time Page Mode Data Transfer
DRAM Interface C128 C129 C130
CAS pre-charge pulse width CAS low-level pulse width RAS hold time
tCP tCAS tRSH
1 1 1
cycle cycle cycle
DRAM Interface CAS Before RAS Refresh C131 C132 C133 CAS-RAS delay time Refresh RAS low-level pulse width tCRD tRRAS 1 4 cycle cycle
Refresh CAS low-level pulse width tRCAS 5 cycle A11 and A10 indicate the output from MON pin and NCAS1 pin respectively. One cycle is the system clock cycle of 1 / (16.9344 MHz or 33.8688 MHz) [s]. The system clock frequencies, 16.9344 MHz and 33.8688 MHz, are determined according to the IC's DRAM interface clock frequency.
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MN662792AB
DRAM Access Timing (NRAS, NCAS0, NCAS1, NEW, A0 to A9, D0 to D3) A11 to A0
tASR Row Address tRAH Column Address tASC tCAH
NRAS
NCAS0/NCAS1
tRCD
[READ] NWE (=H) D3 to D0
tRAS tCAC
[WRITE] NWE
tWCS
tWCH
D3 to D0
tDWDS tDWDH
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MN662792AB
A11 to A0
Row Address Column Address Column Address tASC tCAH Column Address
NRAS
tRSH
NCAS0/NCAS1 [READ]
tCP tCAS
NWE (=H)
D3 to D0
tCAC
[WRITE] NWE
D3 to D0
tDWDS tDWDH

NRAS NCAS0/NCAS1
tCRD tRRAS
tRCAS
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Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this material. (4) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (5) The products and product specifications described in this material are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.
2002 JUL

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